The present invention relates to a driving method for a plasma display panel (PDP) and a plasma display apparatus.
In recent years, an AC plasma display apparatus for executing a surface discharge has been commercially available as a flat-type display apparatus, and has been used as a display apparatus for personal computer and work station, etc., a flat-type wall-mounted television, and an apparatus for displaying advertisements, information, and others. Such a plasma display apparatus for executing the surface discharge has a structure in which a pair of electrodes is formed on an inner surface of a front glass substrate and an inert gas is enclosed therein, so that when a voltage is applied between these electrodes, the surface discharges occur on surfaces of a dielectric layer and a protective layer formed on an electrode surface and ultraviolet radiation is generated. On an inner surface of a rear glass substrate, phosphors of three primary colors, red (R), green (G), and blue (B), are applied. By exciting and light emitting these phosphors by ultraviolet radiation, color display is achieved.
FIG. 1 is a block diagram schematically showing an example of a conventional plasma display apparatus and shows an AC driven plasma display apparatus for three-electrode surface discharge. Note that the plasma display apparatus shown in FIG. 1 is merely an example and the present invention described below can be applied to display apparatuses for executing display discharges (sustain discharges), which have various structures other than a structure of the AC driven plasma display apparatus for three-electrode surface discharge shown in FIG. 1.
A plasma display apparatus 100 includes: a PDP 1; an X driver 75, a Y driver 77, and an A driver (address driver) 79 for driving each display cell (discharge cell) 10 of the PDP 1; a control circuit (control block) 71 for controlling these drivers; and a power supply circuit 73.
The PDP 1 is, for example, such that a plurality of pixels having phosphors of R, G, and B are arranged and color display is achieved by exiting and light emitting the phosphors of the respective cells 10 by ultraviolet radiation. The PDP 1 includes X electrodes and Y electrodes provided in a row direction and A (address) electrodes provided in a column direction. These X electrodes, Y electrodes, and A electrodes are controlled by a driver controller 730 and are also driven by the X driver 75, the Y driver 77, and the A driver 79, respectively, connected to the power supply circuit 73.
The control block 71 includes a data conversion circuit 710, a frame memory 720, a driver controller 730, an APC (Auto Power Control) computation circuit 740, and a number-of-pulses table 750. Frame data Df representing luminance levels (input luminance levels) of three colors of R, G, and B from an external device such as a TV tuner or computer, and an unshown dot clock CLK as well as various synchronization signals (a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, and others) are inputted in the control block 71. Note that a frame and a sub-frame are also called a field and a subfield, respectively.
The data conversion circuit 710 converts the frame data Df serving as multivalued image data into sub-frame data Dsf for reproducing gray scale through a combination of binary images. The sub-frame data Dsf is stored in a frame memory 720, and is then transferred to the A driver 79 by the driver controller 730 in accordance with progress of the display and is used for an addressing which makes a charge amount of the cell 10 corresponding to whether the light emission is required.
The APC computation circuit 740 and the number-of-pulses table 750 are components for the APC. The APC computation circuit 740 obtains a display load from the sub-frame data Dsf to define a setting luminance L′ for the maximum level gray scale. The setting luminance L′ represents control information for specifying the number of times of display discharge of the cell that displays the maximum level gray scale.
An allocation of a light emission amount to a plurality of sub-frames (SF) forming one frame (F) is stored in the number-of-pulses table 750, and a display pulse number f for each sub-frame corresponding to the setting luminance L′ is notified of the driver controller 730. In response to this, for display of each sub-frame, the driver controller 730 makes the display discharge being executed up to times equal to the display pulse number f corresponding to the sub-frame. When the setting luminance L′ in the APC computation circuit 740 is determined, a corresponding relation between each level of the gray scale to be displayed and the luminance of the cell, that is, a total number of display pulses to be applied to the cells in one frame for reproducing each level of the gray scale is uniquely defined.
FIG. 2 is a view for explaining a driving sequence in the plasma display apparatus shown in FIG. 1.
In order to make a color display through binary On-state control in driving the PDP 1 of the plasma display apparatus 100, a frame F inputted per predetermined interval is divided into n sub-frames SF1 to SFn. In this case, the sub-frames SF1 to SFn have weights W1 to Wn, respectively and, in accordance with the weight, the number of times of display discharge is determined. Note that the weights W1 to Wn may be determined so as to satisfy powers of two (1, 2, 4, 6, 8, 16, . . . ), but in order to suppress an occurrence of a dynamic false contour associated with the gray-scale display of frame division, various settings can be made, such as a setting in which a plurality of sub-frames having the same weight are included.
To match such a frame structure, a frame period Tf, which is a frame transfer period, is divided into n sub-frame periods Tsf, and one sub-frame period Tsf is assigned to each sub-frame SF. Furthermore, each sub-frame period Tsf is divided into a reset period TR for initializing a wall charge, an address period TA for addressing, and a display period (sustain discharge period) Ts for sustaining an On state. In this case, the length of the reset period TR and the length of the address period TA are constant irrespectively of the weight of the sub-frame SF, whilst the length of the display period TS is longer since the number of times of discharge is increased as the weight of the sub-frame SF is larger.
FIG. 3 is a view schematically showing driving waveforms of the plasma display apparatus shown in FIG. 1. In FIG. 3, suffixes 1 to v attached to the Y electrodes (Y1 to Yv) represent the arrangement order. Note that the driving waveforms shown in FIG. 3 are merely an example, and their amplitudes, polarities, and timing, etc. can vary.
In the reset period TR of each sub-frame SF, ramp waveform pulses of positive and negative polarities are sequentially applied to all of the X electrodes. Also, ramp waveform pulses of positive and negative polarities are sequentially applied to all of the Y electrodes (Y1 to Yv). Note that applying the pulse to the electrode means temporarily biasing of the electrode.
In this case, a combined voltage obtained by totalizing amplitudes of pulses given to the X electrode and the Y electrodes is applied to the cell 10. A micro discharge occurring at a first pulse application makes the wall voltages with the same polarity being generated to all of the cells 10, irrespectively of On/OFF state of the previous sub-frame. Also, a micro discharge occurring at a second pulse application adjusts the wall voltage to a value equivalent to a difference in amplitude between a firing voltage and an applied voltage.
In the address period TA, wall charges required for sustaining the On state are formed only for any cells to be turned On. In a state in which all the X electrodes and all the Y electrodes are biased to predetermined potentials, for every row selection period (scan time for one row), a scan pulse Py is applied to one Y electrode corresponding to the selected row. Simultaneously with this row selection, an address pulse Pa is applied to only an A electrode corresponding to the selected cell that has to generate an address discharge. That is, based on the sub-frame data Dsf of the selected row, the potential of the A electrode is subjected to binary control. For this reason, in the selected cell, a discharge occurs between the Y electrode and the A electrode. Such an occurrence becomes a trigger, which results in an occurrence of a discharge between the X electrode and the Y electrode. A series of these discharges forms an address discharge.
In the display period TS, a display pulse (also called a sustain pulse) Ps is applied alternately to the Y electrode and the X electrode. Therefore, a pulse string whose polarity is alternately changed is applied to the cell. Since this display pulse Ps is applied, the display discharge occurs at the cell in which a predetermined wall charge remains. The number of times of application to the display pulse Ps corresponds to the weight of the sub-frame, and is adjusted in accordance with the display load.
FIG. 4 is a view schematically showing an electrode structure of one cell of one example of the conventional plasma display apparatus. In FIG. 4, the reference numeral “11” denotes a front-side substrate, “12” denotes an X electrode (transparent electrode and bus electrode for X electrode), “13” denotes a Y electrode (transparent electrode and bus electrode for Y electrode), “14” and “17” denote dielectric layers, “15” denotes a rear-side substrate, “16” denotes an address electrode (transparent electrode and bus electrode for A electrode), and “18” denotes a phosphor layer.
As shown in FIG. 4, the X electrode 12 and the Y electrode 13 are provided in parallel on the front-side substrate 11, and further the dielectric layer 14 is formed so as to cover the X electrode 12 and the Y electrode 13. The A electrode 16 is provided on the rear-side substrate 15 in a direction perpendicular to the X electrode 12 and the Y electrode 13 of the opposite front-side substrate 11, and further the dielectric layer 17 and the phosphor layer 18 are formed so as to cover the A electrode 16.
In a spacing 19 between the front-side substrate 11 provided with the X electrode 12 and the Y electrode 13 and the rear-side substrate 15 provided with the A electrode 16, a discharge gas such as a mixture of gases of neon and xenon is charged. A discharge space, which is a crossing portion between the X and Y electrodes 12 and 13 and the A electrode 16, forms one cell 10.
Conventionally, in order to reduce the firing voltage for executing the display discharge, there has been proposed a plasma display apparatus in which a thin auxiliary electrode is provided between the X electrode and the Y electrode and an auxiliary-electrode driving pulse is applied to this auxiliary electrode at a time not later than a time of starting a discharge sustain pulse (display discharge pulse) for driving (for example, see Patent Document 1: Japanese Patent Laid-Open Publication No. 2000-251746). Also, conventionally, there has been proposed a PDP in which a dummy electrode is provided between two sustain electrodes (display electrodes: X electrode and Y electrode) aligned in parallel and, by applying a potential between the potentials of the scan electrode and the sustain electrodes, a crosstalk at a time of writing is reduced (for example, see Patent Document 2: Japanese Patent Laid-Open Publication No. 2002-134033 and Patent Document 3: Japanese Patent Laid-Open Publication No. 2002-352726).
Furthermore, conventionally, a plasma display driving method (for example, see Patent Document 4: Japanese Patent Laid-Open Publication No. 2003-241708) has been proposed as follows. That is, in order to improve luminance and light-emitting efficiency at the display discharge, An addressing for forming the wall charge to the cell to be turned ON is carried out. Thereafter, in order that the cell makes the display discharge and reformation of the wall charge subsequently to it being carried out, the potential of at least one display electrode is varied so that the potential at the time of starting the display discharge is different from that at the time of ending the display discharge and, concurrently, the potential of at least one electrode other than the display electrode is varied so that the potential at the time of starting the display discharge is different from that at the time of ending the display discharge.
Still further, conventionally, a display device driving method and an image display apparatus have been proposed (for example, see Patent Document 5: Japanese Patent Laid-Open Publication No. 2004-191610) as follows. That is, in order to reduce an unnatural change in brightness occurring when the display load is changed and to achieve stable power control without a sporadic increase in power consumption, when the change in the display load is mild, the light emission amount is slightly changed and the following of the power control with respect to the change in the display load at that time is made slow. Conversely, when the change in the display load is sharp, the light emission amount is significantly changed and the following of the power control at that time is made quick.
Note that conventionally an AC driven PDP has been also proposed (for example, see Non-patent Document 1: “Highly Luminance-efficient AC-PAP with Delta Cell Structure Using New Sustain Waveforms”, SID 03 DIGEST pp. 137-139, issued on May, 2003).